bottlenecks in sampling rate and bandwidth

[virtmax]

Hello,
could the DSO112 designers please explain what the bottlenecks in sampling rate and bandwidth are?
I see that the analog bandwidth of the DSO068 Kit was increased to 3 MHz in comparison to the DSO062 (1 MHz). Is it possible to increase the analog bandwidth also for the DSO112 with some small hardware changes?

Another point is the sampling rate. My understanding is that the sampling rate should be at least two times the analog bandwidth.
The ADC of the DSO112 has a sampling rate of 20 MSPS (http://www.ti.com/lit/ds/symlink/tlc5510.pdf). Why is it not possible to achieve this sampling rate with DSO112? Is it a firmware problem?

[jye1]

The main limiting factor is MCU speed because transfering of data from ADC to memory is completed by software. currently the higheat real time sampling rate we can achieve is 5MSPS without handling trigger or 2MSPS with trigger handled. Use higher speed processor will increase through-put and as a result achieve higher sampling rate, which in turn allows wider analog bandwidth.

[davef]

Use higher speed processor will increase through-put ...

or DMA?

[jye1]

DMA is faster sometimes. But AVR doesn't have DMA feature.

[virtmax]

Thanks for the reply.
So, if I replace 20 MHz oscillator by 25 MHz one (I heard that Atmega64 works even at 28 MHz) can I achieve 20% better sampling rate?
Can the firmware handle this change or is the oscillation frequency hardcoded?

[jye1]

Unfortunately it was hardcoded. The sampling rate is strictly dependent on instruction cycles.